<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title>Bing: Bayesian Algorithm Optimisation</title><link>http://www.bing.com:80/search?q=Bayesian+Algorithm+Optimisation</link><description>Search results</description><image><url>http://www.bing.com:80/s/a/rsslogo.gif</url><title>Bayesian Algorithm Optimisation</title><link>http://www.bing.com:80/search?q=Bayesian+Algorithm+Optimisation</link></image><copyright>Copyright © 2026 Microsoft. All rights reserved. These XML results may not be used, reproduced or transmitted in any manner or for any purpose other than rendering Bing results within an RSS aggregator for your personal, non-commercial use. Any other use of these results requires express written permission from Microsoft Corporation. By accessing this web page or using these results in any manner whatsoever, you agree to be bound by the foregoing restrictions.</copyright><item><title>Intel Unified Login</title><link>https://community.intel.com/t5/Intel-Quartus-Prime-Software/Modelsim-work-empty-problem/m-p/1664212</link><description>Discusses a problem with ModelSim in Intel Quartus Prime software and seeks solutions from the community.</description><pubDate>Mon, 22 Jun 2026 02:22:00 GMT</pubDate></item><item><title>Modelsim: compiling into libraries - Intel Community</title><link>https://community.intel.com/t5/Programmable-Devices/Modelsim-compiling-into-libraries/td-p/137175</link><description>Hi all, I've a few questions regarding Modelsim: 1) libraries contain the VHDL files or the result of the compilation of these files? 2) How can I compile a file in a directory by my choice, different from the work directory? 3) In a testbench, i saw this: library work; use work.lib_o...</description><pubDate>Thu, 09 Jan 2025 07:27:00 GMT</pubDate></item><item><title>Submit Form - Intel Communities</title><link>https://community.intel.com/t5/Intel-FPGA-Software-Installation/modelsim-license/td-p/1451822</link><description>&lt;strong&gt;Note:&lt;/strong&gt; Since your browser does not support JavaScript, you must press the Resume button once to proceed.</description><pubDate>Sat, 13 Jun 2026 11:58:00 GMT</pubDate></item><item><title>OpenCL RTL simulation using ModelSim-Intel FPGA Edition or Aldec ...</title><link>https://community.intel.com/t5/Intel-High-Level-Design/OpenCL-RTL-simulation-using-ModelSim-Intel-FPGA-Edition-or-Aldec/m-p/1271480</link><description>I have ModelSim-Intel FPGA edition and Aldec Riviera Pro simulator in my system.I donot have MentorGraphics ModelSim with me. When I am simulating the vector_add OpenCL example design using the following procedure.</description><pubDate>Wed, 23 Jul 2025 01:13:00 GMT</pubDate></item><item><title>Quartus ModelSim Memory allocation failure - Intel Community</title><link>https://community.intel.com/t5/Intel-Quartus-Prime-Software/Quartus-ModelSim-Memory-allocation-failure/td-p/663010</link><description>Windows 10 with 25GB available RAM and plenty of swap space. My design is SIGNIFICANTLY smaller than the 10K executable code line limit for the Intel-FPGA ModelSim Starter edition unless some ALTCLKCTRL and ALTPLL IP modules involve 1000s of "executable lines". Using Verilog. My individual modules...</description><pubDate>Wed, 09 Jul 2025 05:26:00 GMT</pubDate></item><item><title>Do I need a license for code coverage in Modelsim?</title><link>https://community.intel.com/t5/Intel-FPGA-Software-Installation/Do-I-need-a-license-for-code-coverage-in-Modelsim/td-p/700950</link><description>Modelsim-Altera Edition and Starter Edition do not support code coverage feature, customer must use other simulation tool such as ModelSim* PE/DE software or Questa* advanced simulator.</description><pubDate>Fri, 28 Mar 2025 18:27:00 GMT</pubDate></item><item><title>how to see all signals without optimization in modelsim 10.7</title><link>https://community.intel.com/t5/Intel-Quartus-Prime-Software/how-to-see-all-signals-without-optimization-in-modelsim-10-7/td-p/188466</link><description>I'm simulating with modelsim 10.7 a design created with Quartus Prime Pro 18, but I don't know hot to do the simulation with no optimizations with this new version. I attach the simScript.do where now is the -O0 option I'v tried multiple options from vopt but without success. So, what I'm doing wr...</description><pubDate>Sat, 22 Mar 2025 03:39:00 GMT</pubDate></item><item><title>Creating a waveform in Modelsim - Intel Community</title><link>https://community.intel.com/t5/Programmable-Devices/Creating-a-waveform-in-Modelsim/td-p/174002</link><description>The Modelsim wave editor produces a VHDL or Verilog file that you then need to connect to your logic. So the only step you are 'changing' by using the waveform editor is that you are manually creating the waveforms using a graphical editor, rather than typing in VHDL. I can understand that using Qsim looks to be easier.</description><pubDate>Fri, 08 Aug 2025 23:13:00 GMT</pubDate></item><item><title>Solved: Modelsim version compatible with Quartus Prime 18.0.1 Build 261 ...</title><link>https://community.intel.com/t5/Intel-Quartus-Prime-Software/Modelsim-version-compatible-with-Quartus-Prime-18-0-1-Build-261/td-p/193878</link><description>Which Modelsim version is compatible with Quartus Prime 18.0.1 Build 261 06/28/2018 SJ Pro Edition? I am not able to find this info om the website.</description><pubDate>Mon, 24 Mar 2025 08:59:00 GMT</pubDate></item><item><title>Modelsim Zoom in and out - Intel Community</title><link>https://community.intel.com/t5/Intel-Quartus-Prime-Software/Modelsim-Zoom-in-and-out/td-p/153387</link><description>Hi, Have you ever tried with Modelsim to make a zoom-in for a certain range while keeping other ranges zoomed out? I mean I have a waveform for a frame transmitted. I want to zoom-in the begin and the end of the frame while keeping the data payload zoomed out. Is it possible to make that by Mode...</description><pubDate>Tue, 01 Oct 2024 02:38:00 GMT</pubDate></item></channel></rss>