Sometimes design abstraction is a help, and sometimes it's a hindrance. Verification of system-on-a-chip designs with SystemC has a demonstrated ability to significantly speed up simulation runs.

Henderson, Nevada - December 27, 2004-- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new ...

SAN FRANCISCO — Summit Design Inc. has introduced an integrated development environment (IDE) for SystemC-based analysis and debug. The tool, Vista 1.1, is an improved version of the Vista IDE that ...

Availability of hardware for embedded software development is generally delayed as the hardware development cycle takes longer to complete. An integrated setup of an executable specification of the ...

SANTA CRUZ, Calif. — Expanding its capabilities for mixed-language simulation of ASICs and FPGAs, Aldec Corp. this week (Dec. 27) announced the release of Riviera 2004.12. New features include ...

ARM is putting its weight behind SystemC as the much-needed industry standard design and verification language to support designers of multi-sourced intellectual property (IP). “Adopting IP is about ...

An increasing number of embedded designs are multi-core systems. At the pre-silicon stage, customers use a simulation platform for architectural exploration and software development. Architects want ...